Research

Presents SECDA-based generation of FPGA accelerators aimed at reducing manual effort in accelerator design. Explores how structured design tooling and automation can produce hardware that meets practical deployment constraints.

Investigates device-aware distillation techniques that adapt small language models to edge hardware constraints, improving efficiency while preserving useful task performance on constrained devices.

Introduces SECDA-DSE, a framework that integrates large language models into the SECDA methodology for automated design space exploration of FPGA-based accelerators. Combines a structured DSE Explorer for accelerator configurations with an LLM stack that uses retrieval-augmented generation and chain-of-thought prompting, plus a feedback loop for reinforced fine-tuning.

Presents efficient AI models for human activity recognition optimized for low-power edge devices. Demonstrates significant improvements in energy efficiency while maintaining accuracy.

Examines fairness of large language models when deployed in resource-constrained environments compared to cloud or desktop settings. Identifies specific biases that emerge in edge deployments and proposes mitigation strategies.

Introduces novel tiny ML techniques for human activity recognition that achieve high accuracy on microcontrollers and low-power processors. Includes optimization strategies for memory and computational constraints.

Comprehensive survey of phishing prevention techniques, analyzing historical approaches and proposing future directions. Covers technical, educational, and policy-based solutions.

Presents an integrated system for institutional recommendation and ranking using comprehensive datasets and advanced analysis techniques. Demonstrates improved accuracy in educational institution matching and ranking.